Test-point insertion efficiency analysis for LBIST applications

Abstract

Test points are inserted into integrated circuits to increase fault coverage especially in logic built-in self-test (LBIST) schemes. Commercial tools have been developed over the past decade to insert test points in circuits under test, but they are often inefficient and incur unacceptably large area overhead. Our analysis shows that many test points have little or no impact on test coverage. Therefore, we propose a framework to evaluate test point's impact on a design and rank them based on their efficiency, and to obtain an optimal configuration of the most efficient test points accurately and rapidly. Within this framework, we have two metrics; namely the efficient test point insertion (ETPI) metric and the test point removal estimation (TPRE) metric. The ETPI metric is developed to remove the most inefficient test points inserted in the circuits by the commercial tools, thereby minimizing area penalty with very limited test coverage loss. The TPRE metric is introduced to quickly select the appropriate test point removal scheme. Since TPRE can estimate area overhead and test coverage for designs with different percentage of test points removed without the actual insertion of test points and without the need for lengthy circuit simulation, large amount of processing time is saved especially for large circuits. Experimental results indicate that ETPI can reduce area overhead reduction by up to 95.00% with test coverage reduction as low as 0.57%. In addition, results by applying the TPRE metric indicate that the difference between estimation and actual simulation/synthesis results for area overhead is less than 0.10% for most cases, and the difference between them for test coverage is less than 1.00% for most cases.