Abstract
The dataflow model and control-flow model are generally viewed as two extremes of computation models on which a spectrum of architectures are based.In this paper, we present a hybrid architecture model which employs conventional architecture techniques to achieve fast pipelined operation, while exploiting fine-grain parallelism by data-driven instruction scheduling. A mechanism for supporting concurrent operations of multiple instruction threads on the hybrid architecture model is presented and a compiling paradigm for dataflow software pipelining which efficiently exploits loop parallelism in loops is outlined. Simulation results attest that hybrid evaluations can indeed be beneficial.
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