Abstract
In this paper, we present an efficient hybrid architecture model which employee (1) a conventional architecture technique to achieve fast pipelined instruction execution, while exploiting fine-grain parallelism by data-driven instruction scheduling; (2) an efficient mechanism which supports concurrent operation of multiple instruction threads on the hybrid architecture model; (3) a compiling paradigm for dataflow software pipelining which efficiently exploits loop parallelism through limited balancing. We establish a set of basic results which show that the fine-grain parallelism in a loop exposed through limited balancing can be fully exploited by a simple greedy runtime data-driven scheduling scheme, achieving both time and space efficiency simultaneously. Simulation results are briefly discussed. This architecture model is utilized as a research vehicle to study various architecture issues for hybrid dataflow computers, as well as compiling techniques for such machines.
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