Towards a standard flow for system level power modeling

Abstract

Power efficiency is a key design objective for most SoCs today and designers continue to search for new approaches to low power design. As transistor level, gate level and RTL methods have become well understood and widely adopted, interest has grown in power aware system design. This interest has arisen along with the overall growth and adoption of SystemC for functional modeling and simulation. In a comprehensive power aware flow, power analyses and optimizations occur during all three major design phases: System Design, RTL Design, and Implementation. These activities require models that represent the power characteristics of each design element. However, unlike RTL Design and Implementation, System Design has no standard power modeling or analysis mechanisms. This lack of abstract, system level power models inhibits system level power analysis: where models are unavailable the flow is unrealized, where models are available the accuracy and flexibility is often limited. This issue motivated the development of modeling capabilities for IP block abstract power models for use in all phases of SoC design. This development built upon existing gate level modeling semantics and flows. This presentation will begin with an overview of existing gate level power modeling capabilities, using the Liberty modeling language as the example. The interpretation of the models by power calculation applications will be described, including the interaction between power models and simulation data. Requirements beyond the existing gate level capabilities will be described. Key requirements include black-box and grey-box modeling styles, methods for handling the exponential explosion of power states and power state transitions, automatic model generation, power component categorization, and descriptions of power structure and power operation. Some of these requirements have already been implemented while others are in the proposal stage. Example usage of such a system level model will be illustrated with a Transaction Level (TLM) Simulation. The example will illustrate how the model is used to produce dynamic and leakage power calculations from the TLM simulation data.