Abstract
Loop pipelining (LP) is a key optimization in modern high-level synthesis (HLS) tools for synthesizing efficient hardware datapaths. Existing techniques for automatic LP are limited by static analysis that cannot precisely analyze loops with data-dependent control flow and/or memory accesses. We propose a technique for speculative LP that handles both control-flow and memory speculations in a unified manner. Our approach is entirely expressed at the source level, allowing a seamless integration to development flows using HLS. Our evaluation shows significant improvement in throughput over standard LP.
Highlights
FPGA accelerators benefit from excellent energy/performance characteristics, their usage is hindered by the lack of high-level programming tools
The main reason is that existing loop pipelining techniques rely on static schedules, which cannot precisely capture data-dependent behaviors. We address this limitation through a speculative loop pipelining framework supporting both control-flow and memory dependence speculation
This allows our approach to be seamlessly integrated into HighLevel Synthesis (HLS) design flows providing two key benefits: (i) the pipelined datapath is synthesized by the HLS tools that are capable of deriving efficient designs, and (ii) we do not compromise on the ease-of-use aspects: programmers keep all the productivity benefits of having high-level specifications
Summary
FPGA accelerators benefit from excellent energy/performance characteristics, their usage is hindered by the lack of high-level programming tools. The usage of HLS tools resembles that of CAD tools, such as Logic/RTL synthesizers, where the design process involves a lot of interactions with the user These interactions allow the exploration of performance and area trade-offs in the resulting hardware. An important strength of our work is that the speculative design is expressed entirely at the source-level This allows our approach to be seamlessly integrated into HLS design flows providing two key benefits: (i) the pipelined datapath is synthesized by the HLS tools that are capable of deriving efficient designs, and (ii) we do not compromise on the ease-of-use aspects: programmers keep all the productivity benefits (e.g., easier/faster testing) of having high-level specifications. This article was presented in the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems 2020 and appears as part of the ESWEEK-TCAD special issue
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