Abstract
Recently, the critical compliance testing (CT) problem for reduced instruction set computer (RISC)-V has received significant attention. However, control and status registers (CSRs), which form the backbone of the RISC-V privileged architecture specification, have been mostly neglected in the CT effort so far. In this letter, we first analyze the RISC-V privileged architecture specification in detail to group the CSRs into different classes according to their functionality. Based on the classes and additional common CSR characteristics, we come up with a set of fundamental CSR tests. These partly automatically generated CSR tests allow to check the compliance of RISC-V simulators and cores. We found several unknown errors in numerous RISC-V simulators. The results demonstrate the necessity for extensive CSR testing to ensure compliance with the RISC-V specification.
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