Toward Accurate Timing Analysis for Transistor-Level Programmable Fabrics

Abstract

Transistor-level programmable fabrics [3] [4] have received interest recently as more compact embedded field-programmable gate arrays (eFPGAs) for hardware obfuscation, in which a crucial part of the design is implemented in the eFPGA and the rest of the design is implemented as an ASIC. However, conventional static timing analysis (STA) tools were developed either for ASICs or look-up table (LUT)-based FPGAs. Transistor-level programmable fabrics have pass transistors, keepers, and repeaters in the interconnect. Conventional STA tools require the interconnect parasitics to be expressed in SPEF (Standard Parasitic Exchange Format), consisting only of wiring parasitics. Furthermore, logic gates for transistor-level programmable fabrics may have a separate input to the pMOS pull-up network and the nMOS pull-down network. Dual inputs in this manner cannot be handled accurately enough since conventional methods have to take the longest delay among the inputs, which often overestimates the downstream delay. We propose an instance-based characterization solution which enables the use of an STA tool (PrimeTime from Synopsys) for static timing analysis of transistor-level programmable fabrics. We individually characterize each cell (logic gate) instance in the transistor-level programmable fabric, from predecessor cell-instance output to characterized cell-instance output, including all parasitics, pass transistors, repeaters and keepers. Experimental results corroborate that the proposed instance-based characterization method yields very accurate STA for transistor-level programmable fabrics.