Total Area Current Distribution Analysis During UIS Test For 600 V Power Diode By Lock-In Thermography

Abstract

The power semiconductor devices market is pushing for the development of power diodes with a superior robustness in avalanche conditions. This requirement becomes crucial in those applications where the load is an inductance. Therefore, the unclamped inductive switching (UIS) test is commonly adopted for the validation of a new design. When the device under test (DUT) exhibits a reduced avalanche capability, the lock-in thermography (LIT) is a powerful characterization tool for the analysis of the current distribution over the whole device during the UIS test. In this work, the current distribution over the whole area of a 600 V Power Diode during the UIS is investigated by means of the LIT. A complex current distribution dynamics before the device failure arises from the LIT measurements and the experimental temperature maps are here presented.