Topography simulations for contact formation involving reactive ion etching, sputtering and chemical vapor deposition

Abstract

With the shrinking design rule of semiconductor devices, the aspect ratios of contact holes that connect transistor electrodes to wirings have exceeded 10 at a design rule less than 0.15μm. The contact is formed through sequential processes of reactive ion etching (RIE), TiN sputtering, and tungsten chemical vapor deposition (W–CVD). In such a formation process, a contact hole with a large bottom diameter is required to reduce contact resistance. We developed a contact simulation method for optimizing contact formation. This contact simulation involves sequential simulations of RIE, TiN sputtering, and W–CVD processes, which adopt a particle model based on the Monte Carlo method. These topography simulations were calibrated using experimental results, and each simulation was combined in order to calculate these sequential simulations. We calculated the dependences of etching and W–CVD filling profiles on contact hole depth. The simulation profiles of etching and W–CVD filling were in agreement with the experimental results. The sequential simulations showed that W disconnection occurs at over 2.5μm contact depth with a aspect ratio of 19.2 and the contact resistance increases markedly.