Abstract
The authors present a high-level design modeling methodology with three modeling levels: a specification level, an interface level, and a functional level. They demonstrate the methodology on a RISC processor design. All models have been implemented in VHDL and simulated on a SPARC 1 workstation using the ZYCAD VHDL simulator, version 1.0a. Experimental results demonstrate the feasibility and usefulness of the methodology. >
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
