Top-down fabrication and electrical characterization of Si and SiGe nanowires for advanced CMOS technologies

Abstract

Gate-all-around (GAA) silicon (Si) nanowires (NW) field effect transistor is today considered as a valuable alternative to FinFET architecture for advanced CMOS devices. Recent advances in characterization and integration have enabled the fabrication of nanowires with diameter below 10 nm. Although nanowires transistors with excellent electrostatic control can be achieved, the nanoscale dimensions induce quantum confinement effects and confer to nanowires electrical properties which differ from bulk Si. Then, low-field electron and hole mobility in Si NW transistors fabricated on (100) silicon-on-insulator (SoI) substrates have been measured over a wide range of NW width (8 nm ≤ W ≤ 220 nm) and height (6 nm ≤ Hfin ≤ 24 nm). A significant increase of hole effective mobility in thick and narrow Si NWs is evidenced along the [110] direction. In contrast, a decrease of NW width results in an electron mobility reduction. An electron mobility enhancement in n-FET NWs is achieved through the use of tensile strained-SoI (sSoI) substrates. As compared to unstrained-Si, +85% electron mobility enhancement is observed in uniaxially tensile strained-Si NW transistors. We have otherwise studied dual-channel CMOS co-integration, with Si channel n-FET and compressively-strained SiGe channel p-FET NWs. For p-FETs, the efficiency of compressive SiGe channels is evidenced for improving hole mobility in nanowires thanks to a Ge enrichment process. As compared to Si channel, the hole mobility is enhanced by 135% in p-FET NWs. Efficiency of compressive SiGe channel is evidenced for ultra-scaled p-FET NWs (LG = 15 nm) with +90% ION current improvement compared to Si. [110]-oriented NWs are shown to be the best candidates to improve electron and hole mobility under uniaxial tensile and compressive strain, respectively. Finally, in order to increase still further the drive current per layout footprint, GAA stacked-nanowire/nanosheet (NS) MOSFET are discussed in this paper. We will present intrinsic performance and design considerations of GAA structures that will allow to make this architecture a competitive solution for futures technology nodes. The key technological challenges (such as 3D integration process including inner spacer and strain engineering) will be discussed in relation to recent research results. We will show that more flexibility can be achieved with stacked-nanosheet transistors in order to manage power and performance optimization.