Electron and Phonon Engineered Nano- and Heterostructures for Increased Speed and Performance Enhancement of the Electronic and Optoelectronic Devices

Abstract

Abstract : In this project we (i) developed an innovative method for the electron (hole) mobility enhancement using controlled modification of the phonon dispersion in nanoscale structures; (ii) carried out theoretical and simulation work for establishing the nanowire structure parameters required for the phonon engineered electron mobility enhancement; (iii) minimized the thermal resistance of the phonon-engineered structures to achieve better heat removal; and (iv) carried out proof-of-concept measurements for nanowire field-effect transistors demonstrating the mobility enhancement. On the final stage of the project, we built and investigated experimentally characteristics of a silicon nanowire (Si-NW) Schottky-barrier (SB) MOSFETs. The dual-gated Si-NW MOSFETs have been fabricated by e-beam lithography on the highly-doped p-type substrate with SiO2 layer serving as global back gate. We achieved the high ON current, high ON-OFF ratio and steeper sub-threshold swing. The mobility extraction employed TCAD Sentaurus device simulator to achieve higher accuracy. The temperature dependence of the carrier transport in NW FETs has also been investigated. All goals of the project have been successfully achieved. The demonstrated phonon and electron engineered nanowire transistors have such potential benefits as higher speed (electron mobility); better heat removal and thermal management; lower power consumption; smaller size and lower noise. The project contributions to the AFOSR mission include the foundation of an innovative technology, which can help to address the increasing need for the integrated multi-modal sensing and reliable communications. Two PhD graduate students involved in the project defended their dissertation and accepted employment at Intel Corporation and Texas Instruments.