Top-down design process for gate-level combinational logic design

Abstract

A pedagogical process for designing gate-level combinational logic circuits is described. The process can be used for either combinational logic circuits or the combinational logic sections of sequential logic circuits. Positive logic signals (active high signals) as well as negative logic signals (active low signals) can be used in the design process. The top-down design process allows the student to draw functional logic diagrams in a rather routine manner using the positive logic convention, or the direct polarity convention. After obtaining functional logic diagrams, realizable logic diagrams can be easily obtained using any of the common off-the-shelf gate types including AND, OR, NAND, and NOR elements with appropriate inverter symbols. The advantage of the top-down design process is that students can very easily understand and implement gate-level combinational logic functions. Examples are provided to illustrate the top-down design process in teaching combinational logic design.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>