Abstract
This article proposes a concept of dynamic profiling reconfigurable instruction set processor (RISP) and related retargetable tool chain support. The tool chain consists of a profiler, a code map per, and a retargetable compiler. Firstly dynamic profiler is employed to obtain hot path for applications. Then hot block is implemented in reconfiguration logic units. After newly designed hardware block is integrated into system, map per supplies a mechanism to map hot blocks to hardware implementations. Retargetable compiler is used for recompilation and regenerating executable binary code. The three modules have been demonstrated on simulation platform separately. Experimental result in previous work has already demonstrated the profiler can reach 97% of accuracy. A prototype code map per shows the feasibility of the mapping mechanism. The simulation results of retargetable compiler shows with the decrease of code size and reconfiguration time, application can still be largely accelerated by RISP processor.
Published Version
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