TOLERANCE DESIGN OF ANALOG CIRCUITS USING A BRANCH-AND-BOUND BASED APPROACH

Abstract

The design of circuits which are robust against variations in operating and process conditions is crucial in today's IC industry. In the analog design flow this problem can be tackled during the sizing of a new circuit. However, hardly any methods are available which support the designer to compute such a robust design if discrete parameters should be considered in this design step. Discrete parameters arise predominantly if a layout-friendly sizing should be computed in the sense that, e.g., a manufacturing grid for the transistor lengths and widths is considered or that transistor multipliers are used to allow the layout of a transistor as multifinger or common centroid structure without applying rounding operations to the carefully computed sizing. This paper presents a new Branch-and-Bound based approach which allows the automatic computation of a robust design using classical and realistic worst case analysis. The results of the sizing of three circuits show that the new approach is highly efficient. The robustness of the results computed by the new approach is validated by Monte Carlo analyses.