Toggle-Registers Generating in Parallel k kth Decimations of m-Sequences xP+ xk+ 1 Design Tables

Abstract

For the class of primitive trinomials xP+ xk+ 1 with (k, 2P-1) = 1, shift register constructions are presented which are designed to produce in parallel consecutive patterns, of k-consecutive bits each, of the corresponding m-sequence. The resultant class of register structures preserves the function of equivalent feedback shift registers (FSR's) with composite feedback logic while allowing a saving in the physical implementation which amounts to the complete elimination of modulo-2 adders. This accounts for the high-speed performance of the toggle-registers presented, and makes them suitable for a broad range of applications.