Five decade evolution of feedback shift register: algorithms, architectures and applications

Abstract

The accomplishment and insinuation of feedback shift register FSR for the past five decades, lies in the simplest type of digital sequential network circuit with the unit delay can be the physical or the storage element, to deliver a sequence of binary bits, repeat after a period due to the circuit states of finite numbers. The state sequential network by framing the logic for state variable has found wide usage in the sequence or code generation, counting, and sequence recognition or decoding. Thus, the logical design by shifting the registered bits from the physical or storage element exhibits the concept of shift register in the general sequential network. The shift register provided with the suitable feedback logic, capable of generating long string of binary digit possessing quasi-random properties. The high-speed communication cryptography, stream cipher, test pattern generator, image encryption, cyclic redundancy check CRC operation and Bose-Chaudhuri-Hocquenghem BCH encoder require the generation of random numbers in which the FSR have been utilised. This paper addresses a brief overview of the key expansion in the feedback shift register and feedback with carry shift register of either linear or nonlinear with the sequential and/or parallel processing architectures along with their concealed and imminent applications.