Abstract
Power estimation at system-level is essential to address today's growing electronic design challenges with the paradigm shift in embedded SW applications. In this paper, a Virtual Platform (VP) of a commercial MPSoC design is developed and validated through which full-system power consumption can be estimated at Electronic System Level (ESL). The developed VP is modeled in accordance with Transaction Level Modeling (TLM) methodology. The TLM VP contains an Instruction Set Simulator (ISS) of a real multi-core processor that provides instruction-accurate power estimation capability at high simulation speed. In addition, system-level power models for various peripheral controllers in the TLM VP are developed at transaction granularity. Using the Embedded Microprocessor Benchmark Consortium (EEMBC) CoreMark, Dhrystone and Whetstone benchmarks, an average error of 10% in power estimation is achieved as compared to real HW board power consumption.
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