Abstract
The system-on-chip design cost is not only dependent on implementation and manufacturing techniques, but also on the used methodologies and design tools. In recent years, transaction level modelling (TLM) and more specifically the SystemC TLM-2 library has become the standard in writing a system-level specification. Even though TLM-2 based models are more abstract than registry-level ones, they are very challenging to develop. They are often written manually and from scratch. In this paper, we expose a more elaborate and modular structure of transaction level models based on more predictable semantics. This work will be our first stone of the building of a model-driven design, a methodology that has proven itself in software engineering.
Highlights
Over the years, a race is set to elevate the levels of abstraction of systems on chip descriptions to cope with their incessant rise in complexity
Transaction level (TL) models differ from register-transfer level (RTL) models by using neither clock nor signals
We presented a well-structured transaction level model based on SystemC Transaction Level modelling (TLM)-2 library
Summary
A race is set to elevate the levels of abstraction of systems on chip descriptions to cope with their incessant rise in complexity This gives birth to a new field of research called Electronic System Level (ESL). The Interoperability is the main value of this library It is achieved by defining transactions using core interfaces (blocking, nonblocking and direct memory interfaces) between an initiator’s socket and a target’s socket. This establishes a transactional interconnection in which the data passing is carried in the generic payload (GP) format defining standards slots for the information’s attributes.
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