A SysML Profile for Development and Early Validation of TLM 2.0 Models

Abstract

Use of UML for SoC design has recently generated new interest and several UML profiles for SystemC have been developed for this purpose. These profiles, however, do not focus on transaction level modeling (TLM). The TLM 2.0 standard introduces interoperability rules for the correct behavior of component models. The important challenge is to identify and debug errors in the system model occurring due to violation of these rules. In TLM model development based on SystemC or SystemC profiles these rules are usually checked during simulation stage. However, several of these rules are static in nature and can be checked before simulation. In this paper, we present a TLM profile based on SysML and show that it can facilitate in TLM model development and also helps in early validation of TLM 2.0 models by introducing checking of static TLM rules during design phase. Our approach, in effect, contributes to reducing the overall debugging efforts.