Timing Uncertainty For Receivers In Optical Clock Distribution For VLSI

Abstract

Optical interconnection techniques have been suggested to reduce signal skew for clock distribution for silicon VLSI chips. One optical approach for clock distribution is to holographically map an optical signal from an off-chip source to several photoreceivers within small functional cells on a chip surface. Within each functional cell, the clock is distributed via short surface wires with negligible delays. In such a system, the primary source of timing uncertainty is due to fabrication-related variation of transistor parameters between identically drawn receivers on a chip. We present here an overview of the distribution system and two receiver designs. A test chip has been designed and fabricated, and laboratory measurements of transimpedance receiver parameters are presented. Analysis and simulation studies show that a phase-locked loop receiver based on a voltage-controlled ring oscillator can offer two orders of mag-nitude improvement in receiver skew over a simple transimpedance amplifier design, allowing a total synchronization uncertainty on the order of 55 ps while operating at 100 to 200 MHz and requiring much less layout area than the transimpedance amplifier.