Timing Recovery and Adaptive Equalization for Discrete Multi-Tone Signalling in Wireline Applications

Jeremy Cosson-Martin,Hossein Shakiba,Ali Sheikholeslami

doi:10.1109/ojcas.2021.3129929

Jeremy Cosson-Martin, Hossein Shakiba + Show 1 more

Open Access

https://doi.org/10.1109/ojcas.2021.3129929

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Abstract

This paper proposes a discrete multi-tone timing-recovery system with adaptive equalization for ultra-high-speed wireline applications. It combines frequency-domain clock recovery with decision-directed equalization to improve receiver performance while eliminating the need for pilot carriers, thereby increasing spectral efficiency. Compared to a conventional pilot-carrier-based technique employing four pilot carriers and a 32-point FFT, this approach improves phase-error sensitivity by 3.6 times, tracking bandwidth by 1.7 times, increases the jitter tolerance slope by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$20dB$ </tex-math></inline-formula> per decade at low frequency, and removes residual equalization error, resulting in an overall data-rate increase of 27%. The concept is validated at the system-level and gate-level through synthesis in an FPGA. A convergence analysis of both the adaptive equalizer and clock synchronization shows the system’s ability to mitigate error propagation and remain synchronized in the presence of impairments. Finally, we highlight the system’s ability to trade-off clock convergence versus phase error sensitivity. Either parameter can be adjusted by 15 times, optimizing the receiver over a broad range of signal conditions.

Highlights

T HE WIRELINE industry is approaching a turning point
This paper is organized as follows: Section II gives a brief background, Section III investigates the overhead from bin reservation, Section IV describes the proposed receiver, Section V compares the solution to conventional approaches, highlights its frequency tracking capabilities, and discusses its implementation in a Cyclone V Field Programmable Gate Array (FPGA), Section VI analyzes the convergence of both the timing recovery and decision-directed equalizer, and Section VII concludes this paper
This section provides a brief background of Discrete Multi-Tone (DMT) signalling with a focus on equalization and timing recovery

Summary

INTRODUCTION

T HE WIRELINE industry is approaching a turning point. Today’s state-of-the-art 100Gb/s long-reach 4-PAM systems require complex equalization schemes to combat severe Inter-Symbol Interference (ISI) including feed-forward equalizers of 25+ taps [1], [2]. DMT is a mature technology dominant in communication applications that must optimize spectral efficiency This includes low-rate baseband telecommunication systems such as ADSL and VDSL [9], [10] and long-haul optical applications such as single-mode and multi-mode fiber [11], [12]. This paper is organized as follows: Section II gives a brief background, Section III investigates the overhead from bin reservation, Section IV describes the proposed receiver, Section V compares the solution to conventional approaches, highlights its frequency tracking capabilities, and discusses its implementation in a Cyclone V FPGA, Section VI analyzes the convergence of both the timing recovery and decision-directed equalizer, and Section VII concludes this paper

BACKGROUND

PROPOSED EQUALIZER

Findings

CONCLUSION