Timing optimization in SADP process through wire widening and double via insertion

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As the minimum feature size continues to shrink down, the interconnect resistance is getting more important. The wire RC delay now often limits the overall chip performance. In this paper, we address a wire width optimization in self-aligned double patterning (SADP) process, where wire widening and double via insertion are considered simultaneously to minimize the total wire delay of timing critical paths. For each of the wires on the critical paths, the candidate directions to which we enlarge the wire is identified while design rules are taken into account. Each candidate direction is then evaluated in terms of the potential wire delay reduction. We finally select an optimal widening configuration by reducing the problem into a minimum weight independent set (MWIS), which is solved by using an integer learning programming (ILP) solver. Experiments are conducted for a few test circuits; wire resistance is reduced by 22.4%, on average, which allows the clock period to be reduced by 12.5%.