Timing Error Tolerance in Small Core Designs for SoC Applications

Abstract

Timing errors are an increasing reliability concern in nanometer technology, high complexity and multi-voltage\frequency integrated circuits. A local error detection and correction technique is presented in this work that is based on a new bit flipping flip-flop. Whenever a timing error is detected, it is corrected by complementing the output of the corresponding flip-flop. The proposed solution is characterized by very low silicon area and power requirements compared to previous design schemes in the open literature. To validate its efficiency, it has been applied in the design of a MIPS microprocessor core in a 90 nm technology, while a demonstration version of the same core in an FPGA platform is presented.