Cost and power efficient timing error tolerance in flip-flop based microprocessor cores

Abstract

Strengthening failure mechanisms accentuate timing errors as a real threat in nanometer technology microprocessor cores. In this work, we present a low-cost and low-power, multiple timing error detection and correction technique, which is based on a new flip-flop design. This flip-flop exploits a transition detector for error detection along with an asynchronous local error correction scheme to provide timing error tolerance. The proposed and the well known Razor techniques were applied separately in the design of two versions of a 32-bit MIPS microprocessor core using a 90nm CMOS technology. Comparisons based on the experimental results validate the efficiency of the new design approach.