Timing error mitigation in microprocessor cores

Abstract

Timing errors in the memory elements of a design are of increasing importance in nanometer technology microprocessor cores. In this work, we present a flip-flop oriented timing error detection and correction technique. It exploits a transition detector at the input of the flip-flop for error detection along with an asynchronous local error correction scheme to provide timing error tolerance. To validate the proposed approach, it has been applied in the design of a 32-bit MIPS microprocessor core which was fabricated in a 65nm CMOS technology.