Time-to-digital converter (TDC) for WiMAX ADPLL in 40-nm CMOS

Abstract

WiMAX (Worldwide Inter-operability for Microwave Access) is an emerging wireless technology standard, which enables high-speed packet data access. To anticipate future demands of WiMAX technology, we propose an all-digital phase-locked loop (ADPLL) based frequency synthesizer for the WiMAX RF transceiver. The developed ADPLL targets frequencies from 2.3–2.7 GHz and from 3.3–3.8 GHz for low band and high band, respectively. A key component of the ADPLL is a time-to-digital converter (TDC), which replaces the traditional phase/frequency detector and charge-pump. The TDC implementation in 40-nm CMOS technology is chosen and presented in this paper. The TDC architecture is based on a pseudo-differential structure. The TDC system has been verified at 1.2 V of power supply, 33.868 MHz frequency reference (FREF) clock and 4.25 GHz output RF frequency. It is found that the power consumption is about 2.99 mW without a clock gating scheme, but is expected to be reduced to 0.78 mW with the clock gating scheme. The INL and DNL of the TDC is lower than 0.4 LSB. The TDC resolution is between 10.84–12.55 ps. At the worst case condition, the TDC resolution of 12.55 ps will produce the in-band phase noise better than −95 dBc/Hz as required by WiMAX ADPLL system. The TDC core layout has a silicon area of only 125×11 µm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .