Review on the Evolution of Low-power and Highly-linear Time-to-Digital Converters - TDC

Abstract

Time-to-digital converters (TDC) have been widely used in all-digital phase-locked loops (ADPLL). However, the TDC non-linearity and resolution have negatively impacted the ADPLL performance. A better integration between the TDC and ADPLL would improve the performance of the ADPLL, with a minimum increase in power consumption. This paper addresses the main issues in TDC design providing an overview of published architectures. In particular, the evolution of resolution and non-linearity indicators will be reviewed in detail, since they are the most important figures for proper integration of TDCs in ADPLLs.