Time-delay estimation: two comparative models for distributed on-chip RLC interconnects under ramp excitation

Abstract

In today's very large scale integration (VLSI) circuits based on ultra deep submicron (DSM) process technology, on-chip interconnect plays a dominating role in determining the overall circuit performance, reliability and cost. On-chip interconnects are best modelled as a network of coupled lines. Hence, their delay estimation has to consider the effect of parasitic coupling between the lines, as the noise due to parasitic coupling between signal wires can result in functional failure or logic error by introducing delays into the circuit. If accurate interconnect delay estimation is to be achieved, modelling interconnects as a distributed RLC line is necessary. In this paper, we present two different closed-form analytical models for estimating the time-delay of a distributed RLC interconnect.