Time-Varying Cumulative Damage Recursive Method for Power Semiconductor Devices

Abstract

Accurate simulation of power semiconductor devices failure process is one of the most important means to clarify the failure mechanism and evaluate the device reliability, which is induced by the associated internal temperature gradient acting on the mismatch of coefficients of thermal expansion between adjacent layers and internal temperature gradients. This paper investigates the microstructure change of the new and replaced modules using the CT scanner, which represents that the void distribution of the die-attach solder layer is an important factor to indicate the reliability status of the power semiconductor devices. A multiple physical field model combining time-varying cumulative damage recursive method is proposed to simulate the damage accumulation and the physical failure process based on mesh automatic updated method and material failure formula. The number of cycles to failure, thermal resistance, and junction temperature extracted from power cycling test results are used to validate the accuracy of the parameter variation. The physical outline of the voids is extracted to prove the consistency of the microstructure change. This method is intended for operational management and also provided the foundation for the design and development of power electronic devices with high power and high reliability.