Time-Domain Arithmetic Logic Unit With Built-In Interconnect

Abstract

This paper describes a low-power 1-GHz 4-bit time-domain arithmetic logic unit (ALU) targeting hardware accelerator. This ALU relies on the time-domain computation based on digital-to-time converter, digitally controlled oscillator, time-to-digital converter, and successive approximation register analog-to-digital converter. The interconnect bandwidth limitation addressed by the time-domain and voltage-domain encoding to improve the spectrum efficiency by $8\times $ . Encoder and decoders are part of the computation, and that results in 1-GHz operational speed in 65-nm CMOS consuming 17.75 mW only. Compared to the conventional approach, the proposed time-domain computation achieves significantly lower power and latency for similar area and resolution.