Abstract
Memristors have demonstrated immense potential as building blocks in future adaptive neuromorphic architectures. Recently, there has been focus on emulating specific synaptic functions of the mammalian nervous system by either tailoring the functional oxides or engineering the external programming hardware. However, high device-to-device variability in memristors induced by the electroforming process and complicated programming hardware are among the key challenges that hinder achieving biomimetic neuromorphic networks. Here, a simple hybrid complementary metal oxide semiconductor (CMOS)-memristor approach is reported to implement different synaptic learning rules by utilizing a CMOS-compatible memristor based on oxygen-deficient SrTiO3-x (STOx). The potential of such hybrid CMOS-memristor approach is demonstrated by successfully imitating time-dependent (pair and triplet spike-time-dependent-plasticity) and rate-dependent (Bienenstosk-Cooper-Munro) synaptic learning rules. Experimental results are benchmarked against in-vitro measurements from hippocampal and visual cortices with good agreement. The scalability of synaptic devices and their programming through a CMOS drive circuitry elaborates the potential of such an approach in realizing adaptive neuromorphic computation and networks.
Highlights
Memristors have demonstrated immense potential as building blocks in future adaptive neuromorphic architectures
complementary metal oxide semiconductor (CMOS) circuitry designed for a particular memristor type, inexorable electroforming process causing a high device-to-device variability and associated stochastic nature of resistive switching are hampering the realization of efficient neuromorphic networks[15,16,19]
Though the classical pair-based STDP (p-STDP) models helped to establish a fundamental understanding of the Hebbian synaptic plasticity in several neural systems but it is not sufficient to accurately model all biological experimental results produced by multiple spikes[29,32]
Summary
Memristors have demonstrated immense potential as building blocks in future adaptive neuromorphic architectures. A simple hybrid complementary metal oxide semiconductor (CMOS)-memristor approach is reported to implement different synaptic learning rules by utilizing a CMOS-compatible memristor based on oxygen-deficient SrTiO3-x (STOx) The potential of such hybrid CMOS-memristor approach is demonstrated by successfully imitating timedependent (pair and triplet spike-time-dependent-plasticity) and rate-dependent (Bienenstosk-CooperMunro) synaptic learning rules. Though the classical p-STDP models helped to establish a fundamental understanding of the Hebbian synaptic plasticity in several neural systems but it is not sufficient to accurately model all biological experimental results produced by multiple (triplet and quadruplet) spikes[29,32] This can be associated with deficiencies in the classical p-STDP model, such as excluding non-linear integration of spike pairs and their repetition frequency to quantify the synaptic modification[30,32]. We utilize a well-established CMOS circuit, called forward body biasing[38,39,40,41], in combination with a time-to-digital converter to implement time-dependent synaptic rules and demonstrate the potential of implementing a wide variety of synaptic learning rules
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