Low Power Memristor-Based Shift Register Design

Abstract

The use of memristors is considered to be an appropriate alternative solution to Complementary Metal Oxide Semiconductor (CMOS) technology's scaling limitation. In digital design, shift registers are widely used and considered to be basic memory devices. In this paper, a fast and efficient area memristor-only-based shift register, as well as a hybrid CMOS/memristor-based shift register are proposed. Specifically, a 4-bit shift register with only 8 memristor devices and a hybrid CMOS /memristor with 64 memristor devices and 64 CMOS transistors were implemented and simulated using Cadence Virtuoso. The simulation results demonstrate the design's efficient functionality. Compared to the implementation of a CMOS-memristor based shift register, the implementation of the proposed design is more efficient when concerning area and speed with respect to the implementation of the Memristor Based-Material-Implication (IMPLY) memristive shift register. In addition, the shift register with only memristor-based has a significant power reduction of over 30% compared to a CMOS design shift register.