Abstract
In this paper, we design a THz CMOS on-chip patch antenna with defected ground structure (DGS) and utilize it to implement a broadband and high gain on-chip antenna array. It is verified from the simulation that the DGS not only can increase the gain and bandwidth of the antenna element, but also can increase the isolation between the antenna elements in the on-chip array. Therefore, it allows the design of the compact 1 × 2 and 2 × 2 on-chip antenna array with high gain and broad bandwidth. The element spacing and feedline structures of the antenna array are designed and optimized by the simulations. The designed antenna element, and 1 × 2 and 2 × 2 antenna arrays are fabricated in a commercial 65 nm CMOS process. In the on-wafer measurement, they exhibit an antenna gain of 3.1 dBi, 7.2 dBi, and 8.2 dBi with a bandwidth of 14.0%, 21.3%, and 28.0% for the reflection coefficient less than −10 dB, respectively, at 300 GHz. This result corresponds to very good performance compared to the reported THz CMOS on-chip antenna array. Therefore, the designed CMOS on-chip antenna element and array using DGS in this work can be effectively applied to build low-cost and high performance THz systems, because they can be fully implemented in a conventional CMOS process without requiring any additional processes or manufacturing techniques.
Highlights
There has been extensive research on semiconductor-based terahertz (THz) integrated circuits (ICs) for imaging sensors, radars, and wireless communications [1,2]
It is shown the from the simulations thearray, defected ground structure (DGS) proposed allows a high gain of on-chip antenna array under a compact area
The proposed patch antenna shows the improved bandwidth of 6.0% thanks to the DGS
Summary
There has been extensive research on semiconductor-based terahertz (THz) integrated circuits (ICs) for imaging sensors, radars, and wireless communications [1,2]. CMOS process, and eight antennas were arrayed with was the using Wilkinson power a large chip area. Designed at 260 GHz in a 65 nm CMOS process, and eight element antennas were arrayed with the. The low-loss feedline structures patch to obtain the broadband and high gain antenna element. The low-loss feedline structures areDGS proposed in this work can reduce the coupling between antenna elementsthat in the so that it designed for broadband impedance matches. It is shown the from the simulations thearray, DGS proposed allows a high gain of on-chip antenna array under a compact area. The measured performance is compared to the previously reported THz CMOS on-chip antenna
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