Throughput enhancement for repetitive internal cores in latency-insensitive systems

Abstract

Latency-insensitive design (LID) is a correct by-construction methodology for system on chip design that prevents multiple iterations in synchronous system design. However, one problem in the LID is system throughput reduction. In this study, a protocol is proposed to increase the throughput of internal cores in the latency-insensitive systems when there are several repetitive structures. The validation of the protocol is checked for latency equivalency in various system graphs. A shell wrapper to implement the protocol is described and superimposed logic gates for the shell wrapper are formulated. Simulation is performed for 12 randomly generated systems and four actual systems. The simulation results represent protocol accuracy and show 57% throughput improvement on average compared with the scheduling-based methodology. The protocol also shows area reduction for the majority of simulated systems.