Abstract
Hyper-pipelining is a design technique that results in significant performance and throughput improvements in latency-insensitive designs. Modern FPGA architectures like Intel's Stratix®10 feature a revolutionary register-rich HyperFlex? core fabric architecture that make it amenable for hyper-pipelining. Design implementation CAD tools can provide insights into performance bottlenecks and how hyper-pipelining can result in improved performance, that can then be implemented using well-known techniques like retiming. Retiming was first introduced as a powerful sequential design optimization technique three decades ago, yet gained limited popularity in the ASIC industry. In recent years, retiming has gained tremendous popularity in the FPGA industry. This talk will discuss why this is the case, and provide insights into some of the interesting opportunities it presents for design implementation, analysis, and verification CAD tools. Impacts of hyper-pipelining on the physical design CAD flow and timing closure will also be discussed.
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