Threshold-Voltage Modeling of Double-Gate MOSFETs by Considering Drain Bias

Abstract

Threshold-Voltage Modeling of Double-Gate MOSFETs by Considering Drain Bias Byung-Kil Choi, Kyoung-Rok Han, Young Min Kim, Ki-Heung Park and Jong-Ho Lee School of Electrical Engineering and Computer Science, Kyungpook National University, Daegu 702-701 Tae Moon Roh and Jongdae Kim IT Convergence & Components Laboratory, Electronics & Telecommunications Research Institute, Daejeon 305-700 Threshold-voltage (Vth) modeling of double-gate MOSFETs is very important in the analysis and design of bulk FinFETs or Silicon-On-Insulator (SOI) FinFETs. As drain bias (VDS) increases in double-gate MOSFETs, the charge-sharing length (xh) is increased, resulting in a Vth decrease. The charge-sharing length by VDS is represented by xh;d. The xh;d was modeled as a function of n body thickness and drain bias for a given body doping. The Vth model of double-gate MOSFETs explains well the Vth behavior with n body thickness, body doping concentration, gate length, and drain bias when Drain-Induced-Barrier-Lowering (DIBL) is not dominant. It is also reported that the DIBL should be considered in the Vth model of 20 nm double-gate devices. PACS numbers: 85.30.De