Abstract

We present a 2D physically based compact model of the Double Gate MOSFET, with emphasis on short-channel devices of nanoscale dimensions. A framework model of the drain current modeling has been discussed for the DG device [1-3] and is now expanded to also include the device capacitances. In the sub-threshold regime of a lightly doped DG MOSFET, the electrostatics is dominated by the capacitive coupling between the electrodes. In this regime of operation, the electrostatics of the device can be approximated by the Laplace equation, which can be analytically solved using conformal mapping techniques [1,2]. From this analytical solution, we can calculate the perpendicular electric field along the gate, source and drain electrodes. The electrode charge is found by integrating the perpendicular electrical field along the desired electrode. Finally, the trans-capacitances are obtained from the derivative of the charges with respect to the electrode potentials for all combinations of electrodes and applied potentials at the four terminals. Near and above threshold, the influence of the electronic charge on the electrostatics and the electrode charges is taken into account in a precise, self-consistent manner by combining suitable model expressions with the 2D Poisson’s equation in the device body [3,4]. In this process, the quasi-Fermi potential and the drain current are determined assuming a drift-diffusion transport formalism with constant mobility. For the device considered, this was justified by comparisons with numerical simulations using both hydrodynamic and energy balance transport formalisms. Since short-channel effects are inherently contained in this analysis, no adjustable parameters are needed. The modeling framework covers the full range of bias voltages from subthreshold to strong inversion. The device considered has a gate length of 25 nm and a silicon thickness of 12 nm, permitting the use of classical electron statistics. The device electrostatics, the drain current, and the capacitances calculated from the present models compare very well with numerical simulations using the Atlas device simulator from Silvaco, see figures 1-4.

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