Threshold Voltage Instability Induced by Plasma Process Damage in Advanced Metal–Oxide–Semiconductor Field-Effect Transistors

Abstract

The effects of plasma process-induced physical damage on n-channel metal–oxide–semiconductor field-effect transistor (MOSFET) performance were investigated in detail in terms of threshold voltage (Vth) and Vth shift (ΔVth). The Si recess structure formed by ion bombardment was primarily focused on in this study. Defect site density was also considered as a possible cause of ΔVth. The damaged structure and damage formation mechanisms were studied using an optical analysis technique and classical molecular dynamics simulations. The plasma-induced ΔVth of devices with various recess depths was estimated by technology computer-aided design (TCAD) simulations, by taking into account the bias power dependence of damaged layer thickness. The Vth related to the recess structure shifts toward the negative direction in n-channel MOSFETs, indicating an increase in off-state leakage current (IOFF). |ΔVth| proportionally increases with the increasing recess depth dR (∼ bias power), while the underlying defect density does not affect ΔVth. Moreover, the predicted Vth decrease (ΔVth<0) with an increase in dR strongly depends on gate length (Lg), i.e., the decrement in Vth is inversely proportional to Lg. This suggests that the dR increase induces an exponential increase in the standby power consumption of advanced devices. We provide a comprehensive relationship between device parameters (Vth, Ioff, and Lg) and process parameters for plasma-damaged devices.