Threshold Voltage Control in PMOSFETs with Polysilicon or Fully-Silicided Gates on Hf-Based Gate Dielectric Using Controlled Lateral Oxidation

Abstract

Large threshold-voltage (Vt) shifts are seen in PMOSFETs with Hf-based highK gate dielectric and polysilicon gates. The polysilicon-highK interface can be modified by introducing a thin interfacial oxide layer using a controlled lateral oxidation (CLO) step after gate patterning. This can reduce the threshold voltage shift to within 0.1V of SiO2 reference for devices with gate length <1mm. The benefit of lower Vt with the lateral oxidation comes at the expense of increased EOT. We therefore tried CLO using fully-silicided NiSi gates since the poly-depletion gain can offset the EOT increase. Our results show that the Vt difference between SiO2 and HfSiO is within 50mV. Moreover, the Ion-Ioff performance shows that while poly gates are lower in performance due to high Vt, the FUSI gates give Ion/Ioff at 1.1V of 180 (μA/μm)/20 (pA/μm) for both Hf- silicates and conventional SiO2. Interfacial modification using CLO can be a potential integration solution for highK gate dielectrics with polysilicon gates.