Interface configuration and Fermi-level pinning of fully silicided gate and high-K dielectric stack

Abstract

Metal-induced gap states (MIGS) theory is applied to fully silicided (FUSI) gate for the investigation of Fermi-level pinning at the interface of FUSI gate and high-K dielectrics. Using the combination of semiempirical approach and MIGS theory, it has been found that FUSI gate has effectively MSi2 configuration at the interface with gate dielectrics. The vacuum work function values of several FUSI gates have been obtained through the analysis, and it has also been found that the Fermi-level pinning behavior of FUSI gate on high-K dielectric follows the MIGS theory well. FUSI gate on high-K dielectric shows much weaker Fermi-level pinning compared with polysilicon gate on high K dielectric, which is another attractive advantage of FUSI gate process.