Threshold Voltage and DIBL Variability Modeling Based on Forward and Reverse Measurements for SRAM and Analog MOSFETs

Abstract

A physically based variability model is developed to explain threshold voltage ( $V_{T}$ ) and drain-induced barrier lowering (DIBL) variations, and their correlations for static RAMs (SRAMs) and analog devices fabricated in a 32-nm high- $K$ metal-gate technology. Inputs to the model rely on forward (F) and reverse (R) measurement of transistor pair mismatch. The modeling results are validated on SRAMs and analog devices. Asymmetric and symmetric variation components of $V_{T}$ and DIBL variability are extracted by the model. Asymmetric variation is a major component responsible for the higher $\sigma V_{T}$ mismatch in saturation region compared with linear region, and higher DIBL variability.