Three-Dimensional Stacked Memory System for Defect Tolerance

Abstract

This paper presents a method for constructing a memory system using defective memory chips comprising faulty storage blocks. The three-dimensional memory system introduced here employs a die-stacked structure of faulty memory chips. Signals lines passing through the through-silicon-vias (TSVs) connect chips in the defect tolerant structure. Defective chips are classified into several groups each group comprising defective chips having faulty blocks at the same location. A defect tolerant memory system is constructed using chips from different groups. Defect-free storage blocks from spare chips replace faulty blocks using additional routing circuitry. The number of spare memory chips for defect tolerance is s=$\ulcorner$ ( k × n ) / ( m --- k ) $\urcorner$ to make a system defect tolerant for (n + s) chips with k faulty blocks among m independently addressable blocks.