Three-Dimensional Monolithic FinFET-Based 8T SRAM Cell Design for Enhanced Read Time and Low Leakage

Abstract

FinFETs have replaced planar MOSFETs due to their superior performance, power efficiency, and scalability. However, even FinFETs are expected to reach their scaling limits due to physical limits, process variations, and short-channel effects. As an alternative to device scaling, 3-D integrated circuits (ICs) can increase the number of transistors in a chip in the same footprint area. Among 3-D technologies, monolithic 3-D integration promises the highest density, performance, and power efficiency owing to its high-density monolithic intertier vias. A transistor-level monolithic implementation enables an independent optimization of transistor layers. However, it requires a new 3-D cell library. In this paper, we propose two new 3-D monolithic FinFET-based 8T SRAM cells and compare them with previously reported 6T and 8T SRAM cells implemented in 2-D/3-D. Both the proposed cells use pFinFET access transistors for better area efficiency in 3-D and low leakage current. One of the proposed cells utilizes independent-gate pFinFETs as pull-up transistors whose back gates are tied to the supply voltage for better writeability. This cell has 28.1% and 43.8% smaller footprint area, 31.6% and 43.2% smaller leakage current, and 53.2% and 29.0% lower read time compared with conventional 2-D 6T SRAM and 2-D 8T SRAM cells, respectively.