Three-dimensional Modeling of Core-structured Field Effect Transistor

Abstract

Objective: In our previous publication, a core-structured field effect transistor (CoreFET) device shows field effect transistor (FET) behavior. In this work, we investigated factors such as the thickness of the film and the channel on the conductivity of the device in order to optimize the geometry to provide guidance on the fabrication of the device with the best performance. Methods: This study uses Silvaco ATLAS numerical simulation software to investigate the performance of CoreFET. The effects of the thickness of the dielectric layer, SiO2, and the distance between the drain and source (channel length) on the conductivity of the semi-conductor indium gallium zinc oxide (IGZO) have been studied. The flat FET models with the same parameters were used for comparison. Results: Our simulation results demonstrate a directed correlation between the optimized conductivity of the device and the thickness of the dielectric material, as well as the length of the channel. Enhanced sensitivity is achievable by employing a thinner dielectric layer and a narrower channel. Conclusion: According to the results, the device can achieve better performance by optimizing the thickness of the insulator and the gap distance between drain and source electrodes. The remarkable similarity between them indicates that the FET effect remained largely unaffected by variations in FET shape. This observation suggests a consistent outcome across FETs, reinforcing the notion that CoreFET exhibits comparable results as those of film FETs. This finding significantly broadens the scope of CoreFET applications.