Three-Dimensional Integration Technology Using Self-Assembly Technique and Super-Chip Integration

Abstract

We have proposed a new three-dimensional (3-D) integration technology based on multichip-to-wafer bonding called a super-chip integration. Many chips are simultaneously aligned and bonded onto lower chips using a self-assembly technique in a super-chip integration. It was confirmed that Si chips with sizes of 1 mm square to 5 mm square were precisely assembled on Si wafers with high alignment accuracy of less than 0.5μm. We have fabricated 3-D LSI test chips by a super-chip integration technology.