Abstract
The feasibility of three-dimensional (3D) ultrasound imaging methods that involve computations depends on the performance of a computing system, which requires high-speed image reconstruction. Therefore, we examine the hardware (HW) implementation of the algorithm utilizing a field-programmable-gate-array (FPGA). Subsequently, we analyze the critical path delay of the HW and reduce the delay by modifying the architecture using FPGA resources to increase the maximum frequency.This paper presents a HW implementation approach for performing 3D ultrasound imaging.
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