Three-Dimensional Integration: A Tutorial for Designers

Abstract

There is a perception that classical semiconductor scaling is undergoing saturation and has recently not been delivering on the historical expectations for cost, power, and performance scaling. Both the cost of technology node development and the cost to manufacture the newer nodes have been escalating, as has the nonrecurring engineering charge for new designs in these newer nodes. This has serious implications for our industry's ability to sustain the proliferation of increasingly complex systems at affordable prices and the consequent societal impacts. Thus, the industry has been examining a variety of innovations that scale the package and the board, which have traditionally not scaled to the same extent that silicon has. While silicon has scaled by a factor of 1,000× over the last 45 years, the bump pitch to packages and the trace pitch and ball-grid array pitches on printed circuit boards have scaled by less than a factor of 4× over the same interval, as shown in Figure 1. We are also coming to realize that integrating diverse technologies on a single chip has made technologies far more complex than they need be and to wonder if we could de-integrate technology components, such as memory and logic or analog and logic, and somehow reintegrate them at the system level without loss of latency and bandwidth. In fact, approaches where we optimize technologies for function rather than use general-purpose technologies promise to be lower in cost and achieve better power performance.