Three-Dimensional Chip Stack With Integrated Decoupling Capacitors and Thru-Si Via Interconnects

Abstract

In this letter, the integration of CMOS-compatible thru-Si via (TSV) interconnects with deep-trench decoupling capacitors is demonstrated. Reliability test is performed with a 65-nm CMOS test chip on top of a 3-D Si interposer chip that contains 10 000 TSV interconnects. Multilayer stacking is also demonstrated, and capacitance density of 280 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\hbox{nF/mm}^{2}$</tex></formula> is achieved with two-layer Si interposer chip stacks.