Third-Order Switched-Current Delta-Sigma Modulator with ADC and IDWA

Abstract

This work develops a third-order multi-bit switched-current (SI) delta-sigma modulator (DSM) with a four-bit switched-capacitor (SC) flash analog-to-digital converter (ADC) and incremental data weighted averaging circuit (IDWA). The 4-bit SC Flash ADC is used to improve its resolution, and the IDWA is used to reduce the nonlinearity of digital-to-analog converter (DAC) by moving the thermal noise or system error out of the signal band by first-order noise shaping. The proposed differential sample-and-hold circuit (S/H) exhibits low input impedance with feedback and width-length adjustment in an SI feedback memory cell (FMC) to increase the conversion rate. Measurements reveal that, for a bandwidth of 20 kHz from 5 kHz to 25 kHz, an oversampling ratio (OSR) of 256, a sampling frequency of 10.24 MHz, and a supply voltage of 1.8 V, the signal-to-noise ratio (SNR), dynamic range (DR), effective number of bits (ENOB), power consumption, and chip area are 60.87 dB, 61 dB, 10.11 bits, 18.82 mW, and 0.45 × 0.67 mm2 (without I/O pad), respectively.